Large SDRAMs such as 16 Mbit SDRAMs are typically comprised of two memory banks, which share data output buses, data input buses, and a bidirectional data bus. The input and output buses are coupled to the bidirectional data bus via input and output latches. Each memory bank can be addressed independently.
When testing SDRAMs, testers must be able to write data to and read data from the SDRAMs via the data bus as fast as the SDRAMs are rated, such as with clock speeds of 100 MHz or 200 MHz in some devices. Unfortunately most SDRAM testers have been unable to test SDRAMs at full speed, which makes a manufacturer's guarantee of full data speed specifications unreliable.